The impact of data characteristics and hardware topology on hardware selection for low power DSP

G Keane; J. Spanier; Roger Woods

doi:10.1145/280756.280803

The impact of data characteristics and hardware topology on hardware selection for low power DSP

G Keane
, J. Spanier
, Roger Woods

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there are few detailed results on the choice of multipliers available. This paper considers how the power consumption of a number of multiplier structures such as Carry-Save array and Wallace Tree multipliers varies with data wordlengths and different layout strategies. In all cases, results were obtained from EPIC PowerMill simulations of actual synthesised circuit layouts. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems.

Original language	English
Title of host publication	Proceedings. 1998 International Symposium on Low Power Electronics and Design
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	94-96
Number of pages	3
ISBN (Print)	1581130597
DOIs	https://doi.org/10.1145/280756.280803
Publication status	Published - 01 Jan 1998
Event	Proceedings of the 1998 International Symposium on Low Power Electronics and Design - Monterey, United States Duration: 10 Aug 1998 → 12 Aug 1998

Conference

Conference	Proceedings of the 1998 International Symposium on Low Power Electronics and Design
Country/Territory	United States
City	Monterey
Period	10/08/1998 → 12/08/1998

ASJC Scopus subject areas

General Engineering

Access to Document

10.1145/280756.280803Licence: Unspecified

Cite this

@inproceedings{2edf145f7ce94ff294648e53847c74c6,

title = "The impact of data characteristics and hardware topology on hardware selection for low power DSP",

abstract = "Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there are few detailed results on the choice of multipliers available. This paper considers how the power consumption of a number of multiplier structures such as Carry-Save array and Wallace Tree multipliers varies with data wordlengths and different layout strategies. In all cases, results were obtained from EPIC PowerMill simulations of actual synthesised circuit layouts. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems.",

author = "G Keane and J. Spanier and Roger Woods",

year = "1998",

month = jan,

day = "1",

doi = "10.1145/280756.280803",

language = "English",

isbn = "1581130597",

pages = "94--96",

booktitle = "Proceedings. 1998 International Symposium on Low Power Electronics and Design",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "Proceedings of the 1998 International Symposium on Low Power Electronics and Design ; Conference date: 10-08-1998 Through 12-08-1998",

}

Keane, G, Spanier, J & Woods, R 1998, The impact of data characteristics and hardware topology on hardware selection for low power DSP. in Proceedings. 1998 International Symposium on Low Power Electronics and Design . Institute of Electrical and Electronics Engineers Inc., pp. 94-96, Proceedings of the 1998 International Symposium on Low Power Electronics and Design, Monterey, California, United States, 10/08/1998. https://doi.org/10.1145/280756.280803

The impact of data characteristics and hardware topology on hardware selection for low power DSP. / Keane, G; Spanier, J.; Woods, Roger.
Proceedings. 1998 International Symposium on Low Power Electronics and Design . Institute of Electrical and Electronics Engineers Inc., 1998. p. 94-96.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - The impact of data characteristics and hardware topology on hardware selection for low power DSP

AU - Keane, G

AU - Spanier, J.

AU - Woods, Roger

PY - 1998/1/1

Y1 - 1998/1/1

N2 - Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there are few detailed results on the choice of multipliers available. This paper considers how the power consumption of a number of multiplier structures such as Carry-Save array and Wallace Tree multipliers varies with data wordlengths and different layout strategies. In all cases, results were obtained from EPIC PowerMill simulations of actual synthesised circuit layouts. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems.

AB - Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there are few detailed results on the choice of multipliers available. This paper considers how the power consumption of a number of multiplier structures such as Carry-Save array and Wallace Tree multipliers varies with data wordlengths and different layout strategies. In all cases, results were obtained from EPIC PowerMill simulations of actual synthesised circuit layouts. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems.

U2 - 10.1145/280756.280803

DO - 10.1145/280756.280803

M3 - Conference contribution

SN - 1581130597

SP - 94

EP - 96

BT - Proceedings. 1998 International Symposium on Low Power Electronics and Design

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - Proceedings of the 1998 International Symposium on Low Power Electronics and Design

Y2 - 10 August 1998 through 12 August 1998

ER -

The impact of data characteristics and hardware topology on hardware selection for low power DSP

Abstract

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ASJC Scopus subject areas

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