With the over-provisioned routing resource on FPGA, the topology choice for NoC implementation on FPGA is more flexible than on ASIC. However, it is well understood that the global wire routing impacts the performance of NoC on FPGA because the topology is routed by using fixed routing fabric. An important question that arises is: will the benefit of diameter reduction by using a highly connective topology outweigh the impact of global routing? To answer this question, we investigate FPGA based packet switched NoC implementations with different sizes and topologies, and quantitatively measure the impact of global routing to each of these networks. The result shows that with sufficient routing resources on modern FPGA, the global routing is not on the critical path of the system, and thus is not a dominating factor for the performance of practical multi-hop NoC system. © 2011 IEEE.
|Title of host publication||Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011|
|Number of pages||6|
|Publication status||Published - 01 Jan 2011|
|Event||IEEE Computer Society International Conference on ReConFigurable Computing and FPGAs - Cancun, Mexico|
Duration: 01 Nov 2011 → 01 Nov 2011
|Conference||IEEE Computer Society International Conference on ReConFigurable Computing and FPGAs|
|Period||01/11/2011 → 01/11/2011|