TLM2.0 based timing accurate modeling method for complex NoC systems

Ye Lu; Sakir Sezer; John McCanny

doi:10.1109/ISCAS.2010.5538041

TLM2.0 based timing accurate modeling method for complex NoC systems

Ye Lu, Sakir Sezer, John McCanny

Research output: Chapter in Book/Report/Conference proceeding › Other chapter contribution

1 Citation (Scopus)

Abstract

Scalability and efficiency of on-chip communication of emerging Multiprocessor System-on-Chip (MPSoC) are critical design considerations. Conventional bus based interconnection schemes no longer fit for MPSoC with a large number of cores. Networks-on-Chip (NoC) is widely accepted as the next generation interconnection scheme for large scale MPSoC. The increase of MPSoC complexity requires fast and accurate system-level modeling techniques for rapid modeling and veri-fication of emerging MPSoCs. However, the existing modeling methods are limited in delivering the essentials of timing accuracy and simulation speed. This paper proposes a novel system-level Networks-on-Chip (NoC) modeling method, which is based on SystemC and TLM2.0 and capable of delivering timing accuracy close to cycle accurate modeling techniques at a significantly lower simulation cost. Experimental results are presented to demonstrate the proposed method. ©2010 IEEE.

Original language	English
Title of host publication	Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2900-2903
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5538041
Publication status	Published - 2010
Event	IEEE International Symposium on Circuits and Systems (ISCAS) - Paris, France Duration: 01 May 2010 → 01 May 2010

Conference

Conference	IEEE International Symposium on Circuits and Systems (ISCAS)
Country/Territory	France
City	Paris
Period	01/05/2010 → 01/05/2010

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2010.5538041

R1118ECI: Centre for Secure Information Technologies (CSIT)
McCanny, J. V. (PI), Cowan, C. (CoI), Crookes, D. (CoI), Fusco, V. (CoI), Linton, D. (CoI), Liu, W. (CoI), Miller, P. (CoI), O'Neill, M. (CoI), Scanlon, W. (CoI) & Sezer, S. (CoI)
01/08/2009 → 30/06/2014
Project: Research

Cite this

@inbook{bb1e6de87fe74c66b2c2cb4a5dd6fcbd,

title = "TLM2.0 based timing accurate modeling method for complex NoC systems",

abstract = "Scalability and efficiency of on-chip communication of emerging Multiprocessor System-on-Chip (MPSoC) are critical design considerations. Conventional bus based interconnection schemes no longer fit for MPSoC with a large number of cores. Networks-on-Chip (NoC) is widely accepted as the next generation interconnection scheme for large scale MPSoC. The increase of MPSoC complexity requires fast and accurate system-level modeling techniques for rapid modeling and veri-fication of emerging MPSoCs. However, the existing modeling methods are limited in delivering the essentials of timing accuracy and simulation speed. This paper proposes a novel system-level Networks-on-Chip (NoC) modeling method, which is based on SystemC and TLM2.0 and capable of delivering timing accuracy close to cycle accurate modeling techniques at a significantly lower simulation cost. Experimental results are presented to demonstrate the proposed method. {\textcopyright}2010 IEEE.",

author = "Ye Lu and Sakir Sezer and John McCanny",

year = "2010",

doi = "10.1109/ISCAS.2010.5538041",

language = "English",

pages = "2900--2903",

booktitle = "Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS)",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "IEEE International Symposium on Circuits and Systems (ISCAS) ; Conference date: 01-05-2010 Through 01-05-2010",

}

Lu, Y, Sezer, S & McCanny, J 2010, TLM2.0 based timing accurate modeling method for complex NoC systems. in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS). Institute of Electrical and Electronics Engineers Inc., pp. 2900-2903, IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, 01/05/2010. https://doi.org/10.1109/ISCAS.2010.5538041

TY - CHAP

T1 - TLM2.0 based timing accurate modeling method for complex NoC systems

AU - Lu, Ye

AU - Sezer, Sakir

AU - McCanny, John

PY - 2010

Y1 - 2010

N2 - Scalability and efficiency of on-chip communication of emerging Multiprocessor System-on-Chip (MPSoC) are critical design considerations. Conventional bus based interconnection schemes no longer fit for MPSoC with a large number of cores. Networks-on-Chip (NoC) is widely accepted as the next generation interconnection scheme for large scale MPSoC. The increase of MPSoC complexity requires fast and accurate system-level modeling techniques for rapid modeling and veri-fication of emerging MPSoCs. However, the existing modeling methods are limited in delivering the essentials of timing accuracy and simulation speed. This paper proposes a novel system-level Networks-on-Chip (NoC) modeling method, which is based on SystemC and TLM2.0 and capable of delivering timing accuracy close to cycle accurate modeling techniques at a significantly lower simulation cost. Experimental results are presented to demonstrate the proposed method. ©2010 IEEE.

AB - Scalability and efficiency of on-chip communication of emerging Multiprocessor System-on-Chip (MPSoC) are critical design considerations. Conventional bus based interconnection schemes no longer fit for MPSoC with a large number of cores. Networks-on-Chip (NoC) is widely accepted as the next generation interconnection scheme for large scale MPSoC. The increase of MPSoC complexity requires fast and accurate system-level modeling techniques for rapid modeling and veri-fication of emerging MPSoCs. However, the existing modeling methods are limited in delivering the essentials of timing accuracy and simulation speed. This paper proposes a novel system-level Networks-on-Chip (NoC) modeling method, which is based on SystemC and TLM2.0 and capable of delivering timing accuracy close to cycle accurate modeling techniques at a significantly lower simulation cost. Experimental results are presented to demonstrate the proposed method. ©2010 IEEE.

U2 - 10.1109/ISCAS.2010.5538041

DO - 10.1109/ISCAS.2010.5538041

M3 - Other chapter contribution

SP - 2900

EP - 2903

BT - Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS)

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Symposium on Circuits and Systems (ISCAS)

Y2 - 1 May 2010 through 1 May 2010

ER -

TLM2.0 based timing accurate modeling method for complex NoC systems

Abstract

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ASJC Scopus subject areas

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R1118ECI: Centre for Secure Information Technologies (CSIT)

Cite this