TLM2.0 based timing accurate modeling method for complex NoC systems

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1 Citation (Scopus)

Abstract

Scalability and efficiency of on-chip communication of emerging Multiprocessor System-on-Chip (MPSoC) are critical design considerations. Conventional bus based interconnection schemes no longer fit for MPSoC with a large number of cores. Networks-on-Chip (NoC) is widely accepted as the next generation interconnection scheme for large scale MPSoC. The increase of MPSoC complexity requires fast and accurate system-level modeling techniques for rapid modeling and veri-fication of emerging MPSoCs. However, the existing modeling methods are limited in delivering the essentials of timing accuracy and simulation speed. This paper proposes a novel system-level Networks-on-Chip (NoC) modeling method, which is based on SystemC and TLM2.0 and capable of delivering timing accuracy close to cycle accurate modeling techniques at a significantly lower simulation cost. Experimental results are presented to demonstrate the proposed method. ©2010 IEEE.
Original languageEnglish
Title of host publicationProceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages2900-2903
Number of pages4
DOIs
Publication statusPublished - 2010
EventIEEE International Symposium on Circuits and Systems (ISCAS) - Paris, France
Duration: 01 May 201001 May 2010

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS)
CountryFrance
CityParis
Period01/05/201001/05/2010

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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