Physical unclonable function (PUF) is a promising
security primitive for IP protection and user authentication.
As there are plenty of reconfigurable resources in a field
programmable gate array (FPGA), configurable ring oscillator
(CRO) PUF is one of the most hardware efficient PUF designs.
Previous CRO PUF designs have relatively improved the yield of
challenge and response pairs (CRPs). In this paper, a highly
flexible CRO PUF based on FPGA, defined as Transformer
PUF, is proposed. The proposed PUF design, which has multiple
reconfigurability from XOR gates and multiplexers, can be
deformable between different CRO PUFs. Compared with the
traditional CRO PUFs, it is more resistant to two common
machine learning attack techniques, logistic regression (LR) and
covariance matrix adaptation evolutionary strategies (CMA-ES),
with a small sample set size. Moreover, the Transformer PUF
achieves the highest hardware efficiency among CRO PUFs.
The results of the experiment carried out on Xilinx Artix-7
development board demonstrate that Transformer PUF has a
good uniqueness of 49.44% and a high reliability of 98.12%
|Name||IEEE Workshop on Signal Processing Systems (SiPS): Proceedings|