Ultra-Compact and Robust FPGA-Based PUF Identification Generator

Research output: Chapter in Book/Report/Conference proceedingConference contribution

22 Citations (Scopus)


Physically Unclonable Functions (PUFs), exploit inherent manufacturing variations and present a promising solution for hardware security. They can be used for key storage, authentication and ID generations. Low power cryptographic design is also very important for security applications. However, research to date on digital PUF designs, such as Arbiter PUFs and RO PUFs, is not very efficient. These PUF designs are difficult to implement on Field Programmable Gate Arrays (FPGAs) or consume many FPGA hardware resources. In previous work, a new and efficient PUF identification generator was presented for FPGA. The PUF identification generator is designed to fit in a single slice per response bit by using a 1-bit PUF identification generator cell formed as a hard-macro. In this work, we propose an ultra-compact PUF identification generator design. It is implemented on ten low-cost Xilinx Spartan-6 FPGA LX9 microboards. The resource utilization is only 2.23%, which, to the best of the authors' knowledge, is the most compact and robust FPGA-based PUF identification generator design reported to date. This PUF identification generator delivers a stable range of uniqueness of around 50% and good reliability between 85% and 100%.
Original languageEnglish
Title of host publicationCircuits and Systems (ISCAS), 2015 IEEE International Symposium on
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages5
ISBN (Electronic)9781479983919
Publication statusPublished - 27 May 2015
EventIEEE International Symposium on Circuits and Systems (ISCAS), 2015 - Lisbon, Portugal
Duration: 24 May 201527 May 2015


ConferenceIEEE International Symposium on Circuits and Systems (ISCAS), 2015

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