Using signed digit arithmetic for low-power multiplication

Daniel Crookes, M. Jiang

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)


Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.
Original languageEnglish
Pages (from-to)613-614
Number of pages2
JournalElectronics Letters
Issue number11
Publication statusPublished - 2007

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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