UTILISATION OF BIT LEVEL SYSTOLIC ARRAYS IN WORD LEVEL SYSTEMS.

Research output: Chapter in Book/Report/Conference proceedingOther chapter contribution

Abstract

Bit level systolic array structures for computing sums of products are studied in detail. It is shown that these can be sub-divided into two classes and that, within each class, architectures can be described in terms of a set of constraint equations. It is further demonstrated that high performance system level functions with attractive VLSI properties can be constructed by matching data flow geometries in bit level and word level architectures.
Original languageEnglish
Title of host publicationHighly Parallel Computers
Subtitle of host publicationeds. G L Regins and M Barton
PublisherNorth Holland
Pages191-200
Number of pages10
ISBN (Print)ISBN 0-444-7031
Publication statusPublished - 1987

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    McCanny, J. V. (1987). UTILISATION OF BIT LEVEL SYSTOLIC ARRAYS IN WORD LEVEL SYSTEMS. In Highly Parallel Computers: eds. G L Regins and M Barton (pp. 191-200). North Holland.