Abstract
Bit level systolic array structures for computing sums of products are studied in detail. It is shown that these can be sub-divided into two classes and that, within each class, architectures can be described in terms of a set of constraint equations. It is further demonstrated that high performance system level functions with attractive VLSI properties can be constructed by matching data flow geometries in bit level and word level architectures.
| Original language | English |
|---|---|
| Title of host publication | Highly Parallel Computers |
| Subtitle of host publication | eds. G L Regins and M Barton |
| Publisher | North Holland |
| Pages | 191-200 |
| Number of pages | 10 |
| ISBN (Print) | ISBN 0-444-7031 |
| Publication status | Published - 1987 |