Abstract
In this paper, we propose a framework for minimizing variation-induced timing failures in pipelined designs, while limiting any overhead incurred by conventional guardband based
schemes. Our approach initially limits the long latency paths (LLP s) and isolates them in as few pipeline stages as possible by properly shaping the path distribution. Such a strategy, facilitates the adoption of a special unit that predicts the excitation of the isolated LLP s and dynamically allows an extra cycle for the completion of only these error-prone
paths. Our framework, realized with state-of-the-art tools, finally performs post-layout dynamic timing analysis based on real operands that we extract from a variety of applications. This allows us to estimate the bit error rates under potential delay variations, while considering the dynamic data dependent path excitation. When applied to the implementation of an IEEE-754 compatible double precision floating-point unit (FPU) in a 45nm process technology, the path shaping helps to reduce the bit error rates on average
by 2.71× compared to the reference design under 8% delay variations. The integrated LLP s predict unit and the dynamic cycle adjustment avoid such failures and any quality
loss at a cost of 0.61% throughput and 0.3% area overheads, while saving 37.95% power on average compared to a FPU
with pessimistic margins.
schemes. Our approach initially limits the long latency paths (LLP s) and isolates them in as few pipeline stages as possible by properly shaping the path distribution. Such a strategy, facilitates the adoption of a special unit that predicts the excitation of the isolated LLP s and dynamically allows an extra cycle for the completion of only these error-prone
paths. Our framework, realized with state-of-the-art tools, finally performs post-layout dynamic timing analysis based on real operands that we extract from a variety of applications. This allows us to estimate the bit error rates under potential delay variations, while considering the dynamic data dependent path excitation. When applied to the implementation of an IEEE-754 compatible double precision floating-point unit (FPU) in a 45nm process technology, the path shaping helps to reduce the bit error rates on average
by 2.71× compared to the reference design under 8% delay variations. The integrated LLP s predict unit and the dynamic cycle adjustment avoid such failures and any quality
loss at a cost of 0.61% throughput and 0.3% area overheads, while saving 37.95% power on average compared to a FPU
with pessimistic margins.
| Original language | English |
|---|---|
| Title of host publication | 2018 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED): Proceedings |
| Number of pages | 7 |
| Publication status | Published - 08 May 2018 |
| Event | International Symposium on Low Power Electronics and Design - Washington, United States Duration: 23 Jul 2018 → 25 Jul 2018 http://www.islped.org/2018/registration.php#Registration |
Conference
| Conference | International Symposium on Low Power Electronics and Design |
|---|---|
| Abbreviated title | ISLPED |
| Country/Territory | United States |
| City | Washington |
| Period | 23/07/2018 → 25/07/2018 |
| Internet address |
Fingerprint
Dive into the research topics of 'Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment: Case Study on a Floating-Point Unit'. Together they form a unique fingerprint.Student theses
-
Cross-layer instruction-aware timing error mitigation & evaluation for energy-efficient dependable architectures
Author: Tsiokanos, I., Jul 2021Supervisor: Karakonstantis, G. (Supervisor), Woods, R. (Supervisor) & Nikolopoulos, D. S. (External person) (Supervisor)
Student thesis: Doctoral Thesis › Doctor of Philosophy
File
