Virtex FPGA Implementation of a Pipelined Adaptive LMS Predictor for Electronic Support Measures Receivers

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66 Citations (Scopus)

Abstract

High-speed field-programmable gate array (FPGA) implementations of an adaptive least mean square (LMS) filter with application in an electronic support measures (ESM) digital receiver, are presented. They employ "fine-grained" pipelining, i.e., pipelining within the processor and result in an increased output latency when used in the LMS recursive system. Therefore, the major challenge is to maintain a low latency output whilst increasing the pipeline stage in the filter for higher speeds. Using the delayed LMS (DLMS) algorithm, fine-grained pipelined FPGA implementations using both the direct form (DF) and the transposed form (TF) are considered and compared. It is shown that the direct form LMS filter utilizes the FPGA resources more efficiently thereby allowing a 120 MHz sampling rate.
Original languageEnglish
Pages (from-to)86-95
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume13 (1)
Issue number1
DOIs
Publication statusPublished - Jan 2005

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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