The real time implementation of an efficient signal compression technique, Vector Quantization (VQ), is of great importance to many digital signal coding applications. In this paper, we describe a new family of bit level systolic VLSI architectures which offer an attractive solution to this problem. These architectures are based on a bit serial, word parallel approach and high performance and efficiency can be achieved for VQ applications of a wide range of bandwidths. Compared with their bit parallel counterparts, these bit serial circuits provide better alternatives for VQ implementations in terms of performance and cost.
|Number of pages||19|
|Journal||Journal of VLSI signal processing systems for signal, image and video technology|
|Publication status||Published - 01 Jun 1995|
Bibliographical noteCopyright 2007 Elsevier B.V., All rights reserved.
Yan, M., McCanny, J. V., & Hu, Y. (1995). VLSI architectures for vector quantization. Journal of VLSI signal processing systems for signal, image and video technology, 10(1), 5-23. https://doi.org/10.1007/BF02407023