VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform

Paul McCanny, John McCanny, Shahid Masud

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a JPEG-2000 compliant architecture capable of computing the 2 -D Inverse Discrete Wavelet Transform. The proposed architecture uses a single processor and a row-based schedule to minimize control and routing complexity and to ensure that processor utilization is kept at 100%. The design incorporates the handling of borders through the use of symmetric extension. The architecture has been implemented on the Xilinx Virtex2 FPGA.

Original languageEnglish
Title of host publicationEuropean Signal Processing Conference
Place of PublicationToulouse
PublisherEuropean Signal Processing Conference, EUSIPCO
Pages51
Number of pages54
Volume3
Publication statusPublished - 27 Mar 2002
Event11th European Signal Processing Conference, EUSIPCO 2002 - Toulouse, France
Duration: 03 Sep 200206 Sep 2002

Conference

Conference11th European Signal Processing Conference, EUSIPCO 2002
CountryFrance
CityToulouse
Period03/09/200206/09/2002

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering

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  • Cite this

    McCanny, P., McCanny, J., & Masud, S. (2002). VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform. In European Signal Processing Conference (Vol. 3, pp. 51). [7072288] European Signal Processing Conference, EUSIPCO.