VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform

Paul McCanny; John McCanny; Shahid Masud

VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform

Paul McCanny, John McCanny, Shahid Masud

Queen's University Belfast

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes a JPEG-2000 compliant architecture capable of computing the 2 -D Inverse Discrete Wavelet Transform. The proposed architecture uses a single processor and a row-based schedule to minimize control and routing complexity and to ensure that processor utilization is kept at 100%. The design incorporates the handling of borders through the use of symmetric extension. The architecture has been implemented on the Xilinx Virtex2 FPGA.

Original language	English
Title of host publication	European Signal Processing Conference
Place of Publication	Toulouse
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	51
Number of pages	54
Volume	3
Publication status	Published - 27 Mar 2002
Event	11th European Signal Processing Conference, EUSIPCO 2002 - Toulouse, France Duration: 03 Sept 2002 → 06 Sept 2002

Conference

Conference	11th European Signal Processing Conference, EUSIPCO 2002
Country/Territory	France
City	Toulouse
Period	03/09/2002 → 06/09/2002

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering

Cite this

@inproceedings{a2bf06b8bb2a40ae95856c477d696219,

title = "VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform",

abstract = "This paper proposes a JPEG-2000 compliant architecture capable of computing the 2 -D Inverse Discrete Wavelet Transform. The proposed architecture uses a single processor and a row-based schedule to minimize control and routing complexity and to ensure that processor utilization is kept at 100%. The design incorporates the handling of borders through the use of symmetric extension. The architecture has been implemented on the Xilinx Virtex2 FPGA.",

author = "Paul McCanny and John McCanny and Shahid Masud",

year = "2002",

month = mar,

day = "27",

language = "English",

volume = "3",

pages = "51",

booktitle = "European Signal Processing Conference",

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note = "11th European Signal Processing Conference, EUSIPCO 2002 ; Conference date: 03-09-2002 Through 06-09-2002",

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T1 - VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform

AU - McCanny, Paul

AU - McCanny, John

AU - Masud, Shahid

PY - 2002/3/27

Y1 - 2002/3/27

N2 - This paper proposes a JPEG-2000 compliant architecture capable of computing the 2 -D Inverse Discrete Wavelet Transform. The proposed architecture uses a single processor and a row-based schedule to minimize control and routing complexity and to ensure that processor utilization is kept at 100%. The design incorporates the handling of borders through the use of symmetric extension. The architecture has been implemented on the Xilinx Virtex2 FPGA.

AB - This paper proposes a JPEG-2000 compliant architecture capable of computing the 2 -D Inverse Discrete Wavelet Transform. The proposed architecture uses a single processor and a row-based schedule to minimize control and routing complexity and to ensure that processor utilization is kept at 100%. The design incorporates the handling of borders through the use of symmetric extension. The architecture has been implemented on the Xilinx Virtex2 FPGA.

UR - http://www.scopus.com/inward/record.url?scp=84960882691&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84960882691

VL - 3

SP - 51

BT - European Signal Processing Conference

PB - Institute of Electrical and Electronics Engineers Inc.

CY - Toulouse

T2 - 11th European Signal Processing Conference, EUSIPCO 2002

Y2 - 3 September 2002 through 6 September 2002

ER -

VLSI design and implementation of 2-D Inverse Discrete Wavelet Transform

Abstract

Conference

ASJC Scopus subject areas

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