TY - JOUR

T1 - VLSI module for high-performance multiply, square root and divide

AU - McQuillan, S.E.

AU - McCanny, J.V.

N1 - Copyright 2004 Elsevier B.V., All rights reserved.

PY - 1992/11/1

Y1 - 1992/11/1

N2 - A high-performance VLSI architecture to perform multiply-accumulate, division and square root operations is proposed. The circuit is highly regular, requires only minimal control and can be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform any one of these operations. The gate count per row has been estimated at (27n+70) gate equivalents where n is the divisor wordlength. The throughput rate, which equals the clock speed, is the same for each operation and is independent of the wordlength. This is achieved through the combination of pipelining and redundant arithmetic. With a 1.0 µm CMOS technology and extensive pipelining, throughput rates in excess of 70 million operations per second are expected.

AB - A high-performance VLSI architecture to perform multiply-accumulate, division and square root operations is proposed. The circuit is highly regular, requires only minimal control and can be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform any one of these operations. The gate count per row has been estimated at (27n+70) gate equivalents where n is the divisor wordlength. The throughput rate, which equals the clock speed, is the same for each operation and is independent of the wordlength. This is achieved through the combination of pipelining and redundant arithmetic. With a 1.0 µm CMOS technology and extensive pipelining, throughput rates in excess of 70 million operations per second are expected.

UR - http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-0026942846&md5=d5937ac225c6801705b2672430202485

M3 - Article

AN - SCOPUS:0026942846

SN - 0143-7062

VL - 139

SP - 505

EP - 510

JO - IEE Proceedings E: Computers and Digital Techniques

JF - IEE Proceedings E: Computers and Digital Techniques

IS - 6

ER -