### Abstract

A high-performance VLSI architecture to perform multiply-accumulate, division and square root operations is proposed. The circuit is highly regular, requires only minimal control and can be pipelined right down to the bit level. The system can also be reconfigured on every cycle to perform any one of these operations. The gate count per row has been estimated at (27n+70) gate equivalents where n is the divisor wordlength. The throughput rate, which equals the clock speed, is the same for each operation and is independent of the wordlength. This is achieved through the combination of pipelining and redundant arithmetic. With a 1.0 µm CMOS technology and extensive pipelining, throughput rates in excess of 70 million operations per second are expected.

Original language | English |
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Pages (from-to) | 505-510 |

Number of pages | 6 |

Journal | IEE Proceedings E: Computers and Digital Techniques |

Volume | 139 |

Issue number | 6 |

Publication status | Published - 01 Nov 1992 |

### Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.## Fingerprint Dive into the research topics of 'VLSI module for high-performance multiply, square root and divide'. Together they form a unique fingerprint.

## Cite this

McQuillan, S. E., & McCanny, J. V. (1992). VLSI module for high-performance multiply, square root and divide.

*IEE Proceedings E: Computers and Digital Techniques*,*139*(6), 505-510.