Wavelet packet transforms for system-on-chip applications

Shahid Masud, John V. McCanny

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


A methodology for the production of silicon cores for wavelet packet decomposition has been developed. The scheme utilizes efficient scalable architectures for both orthonormal and biorthogonal wavelet transforms. The cores produced from these architectures can be readily scaled for any wavelet function and are easily configurable for any subband structure. The cores are fully parameterized in terms of wavelet choice and appropriate wordlengths. Designs produced are portable across a range of silicon foundries as well as FPGA and PLD technologies. A number of exemplar implementations have been produced.
Original languageEnglish
Pages (from-to)3287-3290
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Publication statusPublished - 01 Jan 2000

Bibliographical note

Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering
  • Acoustics and Ultrasonics


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