Work-in-Progress: Design Space Exploration of Multi-Task Processing on Space Shared FPGAs

High level synthesis frameworks, such as OpenCL, allow effective design space exploration by scaling of resource allocation via simple to use tunable parameters. The same process can be supported in multi-task processing but long synthesis time hinders system analysis and resource management optimization. This work proposes a methodology for simulation of
multi-task processing on FPGA. In doing so, it also supports static spatial partitioning of resources along with a simulator to evaluate this approach. The simulator is based on a multi-dimensional resource fitting model for spatial evaluation and a machine learning based model for memory access. The results show that the simulator has an accuracy of at least
94.5% on average for throughput evaluation while allowing system design evaluation against various parameters.