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In this paper, we present the results of our study on workload-dependent DRAM error behavior within a real server considering various operating parameters, such as the refresh rate, voltage and temperature. We show that the rate of single- and multi-bit errors may vary across workloads by 8x, indicating that program inherent features can affect DRAM reliability significantly. Based on this observation, we extract 249 features, such as the memory access rate, the rate of cache misses, the memory reuse time and the data entropy, from various compute-intensive, caching and analytics benchmarks. We apply several supervised learning methods to construct the DRAM error behavior model for 72 server-grade DRAM chips by using the memory operating parameters and extracted program inherent features. Our results show that, with an appropriate choice of program features and supervised learning method, the rate of single- and multi-bit errors can be predicted for a specific DRAM module with an average error of less than 10.5 %, as opposed to the 2.9x estimation error obtained for a conventional workload-unaware error model. Our model enables designers to predict DRAM errors in advance for less than a second and study the impact of any workload and applied software optimizations on DRAM reliability.
|Title of host publication||2019 IEEE International Symposium on Workload Characterization: Proceedings|
|Publication status||Early online date - 19 Mar 2020|
|Event||IEEE International Symposium on Workload Characterization - Orlando, United States|
Duration: 03 Nov 2019 → 05 Nov 2019
|Conference||IEEE International Symposium on Workload Characterization|
|Period||03/11/2019 → 05/11/2019|
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R6529CSC: A Universal Micro-Server Ecosystem by Exceeding the Energy and Performance Scaling Boundaries
17/12/2015 → …
Student thesis: Doctoral Thesis › Doctor of PhilosophyFile