XANDAR: verification & validation approach for safety-critical systems

Balmukund Sonigara, Sakir Sezer, Fahad Siddiqui, Raphael Weber, Konstantinos Antonopoulos, Christos Panagiotou, Christos P. Antonopoulos, Georgios Keramidas, Nikolaos Voros, Sena Busra Yengec-Tasdemir, Henry Hui, Kieran McLaughlin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
110 Downloads (Pure)

Abstract

The integration of connected and autonomous technologies in safety-critical brought significant system design challenges. These systems are constantly evolving and becoming more complex. With their connection to the cloud and the internet, these safety-critical systems are now exposed to greater risks of cyber-attacks, which poses new challenges to their safety, reliability and resilience. To approach these complex system design challenges, this paper proposes XANDAR's Verification & Validation strategy using Static Analysis, Timing Analysis, Model-in-loop and Network simulation tool. To ensure functional correctness, the proposed XANDAR Verification and Validation approach utilizes early integration of simulation and static analysis techniques during the development cycle. This proposed approach differs from existing methods by emphasizing early integration, rather than applying it to later stages of development cycle to begin verification. In addition, the proposed approach utilizes timing analysis to ensure non-functional timing aspects meet the timing requirements. The approach applies tools such as Polyspace Bug Finder and Code Prover for static analysis, Timing Architect for timing analysis, NS3 simulator for network architecture simulation. The proposed approach aims to ensure system safety and security through a rigorous and comprehensive verification process. These verification approaches will be validated by applying it to automotive and avionics use cases.

Original languageEnglish
Title of host publicationProceedings of the 36th IEEE International System-on-Chip Conference, SOCC 2023
EditorsJurgen Becker, Andrew Marshall, Tanja Harbaum, Amlan Ganguly, Fahad Siddiqui, Kieran McLaughlin
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Electronic)9798350300116
ISBN (Print)9798350300123
DOIs
Publication statusPublished - 22 Sept 2023
Event36th IEEE International System-on-Chip Conference, SOCC 2023 - Santa Clara, United States
Duration: 05 Sept 202308 Sept 2023

Publication series

Name IEEE International System-on-Chip Conference (SOCC)
Volume2023-September
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference36th IEEE International System-on-Chip Conference, SOCC 2023
Country/TerritoryUnited States
CitySanta Clara
Period05/09/202308/09/2023

Bibliographical note

Funding Information:
This research work was funded by the European Union’s Horizon 2020 Research and Innovation Programme under Grant 957210 (XANDAR).

Publisher Copyright:
© 2023 IEEE.

Keywords

  • Model-in-Loop Simulation
  • Static Analysis
  • Timing Analysis and Network Simulation
  • Validation
  • Verification

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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