YIELD ENHANCEMENT OF BIT LEVEL SYSTOLIC ARRAY CHIPS USING FAULT TOLERANT TECHNIQUES.

J.V. McCanny, J.G. McWhirter

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Methods by which bit level systolic array chips can be made fault tolerant are discussed briefly. Using a simple analysis based on both Poisson and Bose-Einstein statistics authors demonstrate that such techniques can be used to obtain significant yield enhancement. Alternatively, the dimensions of an array can be increased considerably for the same initial (nonfault tolerant) chip yield.
Original languageEnglish
Pages (from-to)525-527
Number of pages3
JournalElectronics Letters
Volume19
Issue number14
Publication statusPublished - 07 Jul 1983

Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.

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