Abstract
With the advent of internet of things (IoT), a significant portion of the computational load is now conducted at remote locations at the network’s edge, supporting an extensive number of new smart applications. The majority of such applications rely on sophisticated data analysis algorithms that must detect or even foresee abnormal situations, aiming to avoid any dramatic consequences of events which might even affect an individual’s health. However, the algorithms involved in these type of applications are computationally intensive thus requiring the utilization of intelligent energy saving techniques to ensure that can be executed on resource constrained IoT devices.Numerous techniques can be utilized to identify patterns by analyzing specific characteristics in the time or frequency domains for a given stimulus. Although frequency domain methods are said to offer deeper insights, they require more computational resources due to a necessary linear transform which is used to perform the desired power spectral analysis (PSA). The choice of this PSA transform results in different power spectral density (PSD) estimation techniques, like the discrete Fourier transform (DFT) which is a common yet computationally intensive method. Consequently, accurately estimating PSD and conducting PSA for an input signal is challenging and the scarcity of research on low-power/complexity algorithm-hardware solutions hinders its broad adoption in power-constrained devices.
This dissertation focuses on the design of energy-efficient PSA systems, motivated by their application in the field of biomedical applications, specifically for heart rate variability (HRV) analysis. An in-depth exploration is conducted into the challenges encountered at various development stages of these systems. Although the main emphasis is on HRV evaluation, it is essential to acknowledge that the insights gained from this thesis regarding PSA systems, extend beyond biomedical applications, which are highlighted throughout the following chapters, emphasizing the broader significance of this research endeavor. To this end, several optimization approaches/frameworks are proposed that can be mapped seamlessly into hardware architectures (facilitating effective hardware-algorithm co-design techniques) or directly applied on embedded devices, aiming to simplify various aspects of the investigated PSA systems. Evidently, such aspects span across various stages of the design process, including algorithmic, hardware architecture, and circuit design phases.
Specifically, the key focus areas of this dissertation are summarized as follows. Initially, the PSD estimation of a non-uniformly spaced time-series is examined, by developing a novel algorithm that improves upon the existing Lomb-Scargle periodogram (LSP)-based PSD estimation methods, using HRV evaluation as a case study. The effectiveness of the proposed algorithm is demonstrated on a real embedded device, using a power profiler that allows to measure the energy dissipation in real-time. Subsequently, this thesis explores advancements in PSA hardware architectures using the fast Fourier transform (FFT), proposing two new approaches for time-frequency analysis (TFA) and PSD estimation of real-valued signals. These developments lead to more energy-efficient algorithm implementations and pipelined architectures that demand less resources. Additionally, to address the high energy consumption of multiplications in PSA systems, innovative multiplier less architectures are introduced at the circuit level that lead to significant chip area and energy savings. Moreover, these proposed multiplier less architectures are coupled with voltage over-scaling (VOS) techniques, so as to simplify the design of multiplier units, and achieve aggressive energy savings by perfectly balancing energy consumption to quality of computations. Finally, this dissertation presents an optimization framework, designed for generating pipelined architectures for the autocorrelation function (ACF) calculation by combining several cross-layer techniques of the previously introduced approaches. These architectures are crucial for autoregressive (AR) PSD estimation, a technique extensively used in various PSA applications and several other digital signal processing (DSP) case studies.
Date of Award | Jul 2025 |
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Original language | English |
Awarding Institution |
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Sponsors | EU Horizon 2020 Marie Sklodowska-Curie ITN Programme |
Supervisor | Georgios Karakonstantis (Supervisor) & Chris Watson (Supervisor) |
Keywords
- power special analysis
- low power hardware architectures
- algorithm-hardware co-design
- low power signal processing hardware architectures