Six-port wireless receiver architectures

  • Xiang Zheng Xiong

Student thesis: Doctoral ThesisDoctor of Philosophy


This work describes novel six-port direct conversion digital receiver architecture.

A general review of six -port reflectometer theory and architectures is presented. Three six-port architectures suitable for MMIC realization are discussed.

A new broadband six-port direct conversion wireless receiver architecture is proposed, designed and characterised. This receiver can operate from 900 MHz to4 GHz and can give bit error rate as low as 8E-7 for input power levels of - 37 dBm without a low noise amplifier. In addition three robust novel methods for the calibration of the six-port digital receiver, which relate to dual-tone calibration. receiver frequency synchronization and dual-tone linearization of on­board diode detector are also proposed.

A modelling strategy for each of the lumped elements required to construct a six-port digital receiver using RFCMOS technology has been studied. Novel models and design rules for CMOS capacitor and inductor design have been given. The various methodologies for the design of a RF CMOS MMIC low noise amplifier are also discussed and a CMOS MMIC low noise amplifier is designed.
Date of AwardJul 2004
Original languageEnglish
Awarding Institution
  • Queen's University Belfast
SupervisorVincent Fusco (Supervisor)

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