FPGA-based Processor Acceleration for Image Processing Applications

    Research output: Contribution to journalArticle

    Published

    View graph of relations

    FPGA-based embedded image processing systems offer considerable computing resources but present programming challenges when compared to software systems. The paper describes an approach based on an FPGA-based soft processor called Image Processing Processor (IPPro) which can operate up to 337 MHz on a high-end Xilinx FPGA family and gives details of the dataflow-based programming environment. The approach is demonstrated for a k-means clustering operation and a traffic sign recognition application, both of which have been prototyped on an Avnet Zedboard that has Xilinx Zynq-7000 system-on-chip (SoC). A number of parallel dataflow mapping options were explored giving a speed-up of 8 times for the k-means clustering using 16 IPPro cores, and a speed-up of 9.6 times for the morphology filter operation of the traffic sign recognition using 16 IPPro cores compared to their equivalent ARM-based software implementations. We show that for k-means clustering, the 16 IPPro cores implementation is 57, 28 and 1.7 times more power efficient (fps/W) than ARM Cortex-A7 CPU, nVIDIA GeForce GTX980 GPU and ARM Mali-T628 embedded GPU respectively.

    Documents

    • FPGA-Based Processor Acceleration for Image Processing Applications

      Rights statement: Copyright 2019 the authors. This is an open access article published under a Creative Commons Attribution License (https://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium, provided the author and source are cited.

      Final published version, 2 MB, PDF-document

    DOI

    Original languageEnglish
    Article number16
    Number of pages22
    JournalJournal of Imaging
    Journal publication date13 Jan 2019
    Issue number1
    Volume5
    DOIs
    Publication statusPublished - 13 Jan 2019

    ID: 163382804